This application claims priority to Japanese Patent Application Number 2000-209122 filed Jul. 10, 2000, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor storage device and a method for evaluating the same. Specifically, the present invention relates to a semiconductor storage device where a deviation of an internal timing for reading data, which results from a variation of characteristics of elements constituting the semiconductor storage device during a fabrication process thereof, can be eliminated after the fabrication process is completed so that an optimum internal timing is obtained, and to a method for evaluating such a semiconductor storage device. Furthermore, the present invention relates to a semiconductor storage device whose specification can be changed after the fabrication thereof is completed so as to provide various types of products (e.g., a product having an 8-bit input/output terminal or a product having a 16-bit input/output terminal), and to a method for evaluating such a semiconductor storage device. Especially, the present invention relates to a semiconductor storage device which is preferably used in the case where semiconductor storage devices based on different supply voltage specifications (e.g., 5 V and 3.3 V) are produced from a same chip design, and to a method for evaluating such a semiconductor storage device.
2. Description of the Related Art
In the semiconductor storage device industry, for the purpose of satisfying various needs of customers, manufacturers supply a line of semiconductor storage devices which have the same storage capacity but different specifications, e.g., the supply voltage for operation (operation supply voltage), the operation speed, the bit width at which data can be input/output at one time, etc. However, even if various types of semiconductor storage devices are produced based on different specifications, these semiconductor storage devices generally have a common circuit configuration, because it is inefficient to design a circuit of a semiconductor storage device in order to realize an optimum configuration for each product type. In order to provide adjustment to various specifications without deteriorating the production efficiency, semiconductor storage devices having a common circuit configuration are fabricated, and means for changing specifications in accordance with necessity is provided to the semiconductor storage devices.
Conventionally, specifications are altered by changing the bonding arrangement or by disconnecting a trimming fuse. Furthermore, using such known methods, a deviation of a specification value from a desired designed value (desired specification value), which results from variation of characteristics caused during a fabrication process, is corrected in a conventional technique.
Change in specifications as to a function of a semiconductor storage device, e.g., the bit width at which data can be input/output at one time, etc., is performed using a logical method which is achieved by switching control circuits related to the function. However, change in specifications regarding performance of a semiconductor storage device, e.g., the operation supply voltage, the operation speed, etc., and correction of a deviation from a desired specification value, require timing adjustments of a synchronization signal for an internal operation of the semiconductor storage device.
A typical synchronization signal used in semiconductor storage devices is an address transition detector (ATD) pulse signal. This signal is a pulse signal generated in response to an externally-supplied address signal, or the like, and used for synchronization of an internal operation. In synchronization with this ATD pulse signal, circuits insides a semiconductor storage device are operated, whereby a high speed operation is achieved. The ATD pulse signal is generated by a synchronization signal generation circuit (hereinafter, xe2x80x9cATD pulse generation circuitxe2x80x9d) in response to an externally-supplied address signal, or the like.
For example, in the case where a semiconductor storage device arranged for use with a 3.3 V supply voltage and a semiconductor storage device arranged for use with a 5 V supply voltage are produced based on a same chip design, if the ATD pulse signal is optimized for a 3.3 V supply voltage specification, the operation speed of the semiconductor storage device is decreased when operated at the supply voltage of 5 V. On the other hand, if the ATD pulse signal is optimized for a 5 V supply voltage specification, the semiconductor storage device does not operate at the supply voltage of 3.3 V. This is because the pulse width of the ATD pulse signal optimized for a 3.3 V supply voltage specification differs from the pulse width of the ATD pulse signal optimized for a 5 V supply voltage specification.
In order to address such problems, in general, the bonding arrangement is changed or the trimming fuse is disconnected, whereby the pulse width of the ATD pulse signal is adjusted such that the semiconductor storage device operates at the supply voltage of 3.3 V.
FIGS. 12 and 13 each show an example of an address input buffer ABUF and an ATD pulse generation circuit ATDPG inside a Static Random Access Memory (SRAM), which is a volatile semiconductor memory, in a conventional semiconductor storage device.
In the semiconductor storage device shown in FIG. 12, the pulse width of the ATD pulse signal is adjusted by utilizing a trimming fuse. Specifically, the potential of an inverter INV13 which connects to an internal timing adjustment signal ITC and a logical threshold adjustment signal VLTC is changed based on whether or not the trimming fuse is disconnected by a laser beam, whereby the pulse width of the ATD pulse signal is adjusted. When the supply voltage is 5 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a high level, the trimming fuse is not disconnected so that the potential input to the inverter INV12 is equal to the supply potential Vcc. When the supply voltage is 3.3 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a low level, the trimming fuse is disconnected by a laser beam so that the potential input to the inverter INV12 is equal to the ground potential GND.
In the semiconductor storage device shown in FIG. 13, the pulse width of the ATD pulse signal is adjusted by changing the bonding arrangement. Specifically, the internal timing adjustment signal ITC and the logical threshold adjustment signal VLTC which control an internal timing of the semiconductor storage device are connected to a bonding pad BPAD. The potential of the bonding pad BPAD is determined by whether the bonding pad BPAD is connected to a power line of a lead frame (i.e., the supply potential Vcc) or a ground line of the lead frame (i.e., ground potential GND), whereby the pulse width of the ATD pulse signal is adjusted. When the supply voltage is 5 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a high level, the bonding pad BPAD is connected to the power line Vcc. When the supply voltage is 3.3 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a low level, the bonding pad BPAD is connected to the ground line GND. An example of such a method for adjusting the pulse width of the ATD pulse signal by changing the bonding arrangement is disclosed in Japanese Laid-Open Publication No. 11-176166.
Next, steps for such an adjustment and change of a specification which are achieved by utilizing a trimming fuse are specifically described below.
In general, a semiconductor storage device includes: electric circuits on a semiconductor substrate, such as transistors, resistors, capacitors, and the like; interconnections which connect such electric circuits to one another; trimming fuses used for changing a circuit configuration after the above circuits and interconnections have been formed, etc.
The semiconductor storage device having such a structure is generally fabricated by successively performing respective steps for forming transistors, interconnections, etc. After all of circuits in the semiconductor storage device have been fabricated, at the final step, specification values of transistors and functions of the semiconductor storage device, such as an operation speed and the like, are measured. If a measured specification value is different from a predetermined (desired) specification value due to variation of characteristics of elements constituting the semiconductor storage device which occurred during the fabrication process, a trimming fuse is disconnected by a laser beam at the final step of the fabrication process, whereby a function such as a reading speed for reading data from a memory of the semiconductor storage device can be adjusted. Furthermore, in a similar manner, another trimming fuse is disconnected by a laser beam in the final step so as to change a circuit configuration, whereby the semiconductor storage device can be specifically arranged so as to be a product based on an 8-bit input/output terminal or a product based on an 16-bit input/output terminal. Furthermore, in the final step of the fabrication process, an appropriate trimming fuse is disconnected by a laser beam so as to change the circuit configuration such that the semiconductor storage device operates in synchronization with an optimum internal timing, whereby the semiconductor storage device can be specifically arranged so as to suitably operate at a specific supply voltage specification, e.g., a 5 V supply voltage specification or a 3.3 V supply voltage specification.
Next, steps for such an adjustment and change of a specification which are achieved by changing the bonding arrangement are specifically described below.
In general, a fabrication process of a semiconductor storage device includes: in the first half of the process, steps for forming electric circuits, such as transistors, resistors, capacitors, and the like, on a semiconductor substrate, and for forming interconnections which connect such electric circuits to one another; and in the second half of the process, steps for connecting these electric circuits and interconnections to external electric elements and for packaging the semiconductor storage device with a resin so as to protect the semiconductor storage device from a physical environment, such as pressure, moisture, etc.
In the second half of the fabrication process, at a step for connecting the semiconductor storage device to an external electric element, the semiconductor storage device is selectively connected (bonded) to an appropriate external connection terminal with a gold wire or the like, whereby the same effect as that achieved by disconnecting a trimming fuse by a laser beam so as to change a circuit configuration can be obtained.
As described above, in a conventional semiconductor storage device having an address buffer and an ATD pulse generation circuit, selection of the supply voltage is determined, for example, between 5 V and 3.3 V, at a bonding step or fuse disconnection step. Thus, this selection cannot be changed after the semiconductor storage device has been packaged.
The step for disconnecting a trimming fuse by a laser beam is carried out during the fabrication process of the semiconductor storage device. Since the semiconductor storage device is coated with a resin or the like in the second half of the fabrication process, a trimming fuse cannot be disconnected after the coating step is completed. Furthermore, similarly, the wire bonding arrangement cannot be changed after the semiconductor storage device has been fabricated because the semiconductor storage device is coated with a resin or the like.
Thus, if a customer changes his/her mind so as to buy semiconductor storage devices arranged for use at a supply voltage of 3.3 V after semiconductor storage devices arranged for use at a supply voltage of 5 V have been fabricated, a manufacturer must carry out the fabrication process from the first step so as to fabricate a fresh set of semiconductor storage devices arranged for use at a supply voltage of 3.3 V. Furthermore, even if a malfunction due to a variation of characteristics of elements constituting the semiconductor storage device which may occur during the fabrication process is detected in a test carried out after the packaging step, there is no way to eliminate such a malfunction. Further still, even if a terminal for achieving a function equivalent to a change of the bonding arrangement or disconnection of a trimming fuse is provided so as to extend outside the package for the purpose of eliminating such a malfunction, a resulting terminal configuration of the semiconductor storage device differs from those of conventional, widely-used semiconductor storage devices. Thus, the customer needs to additionally use a special system for such semiconductor storage devices having extra terminals. Such a semiconductor storage device having an extra terminal outside the package is difficult to handle as compared with widely-used semiconductor storage devices.
According to one aspect of the present invention, a semiconductor storage device includes a rewritable non-volatile semiconductor memory and a volatile semiconductor memory, the non-volatile semiconductor memory including: a memory area for storing timing information for adjusting a timing of an internal operation of the volatile semiconductor memory; and an output circuit for outputting the timing information stored in the memory area to the volatile semiconductor memory, wherein the volatile semiconductor memory adjusts the timing of the internal operation of the volatile semiconductor memory based on the timing information.
In one embodiment of the present invention, the volatile semiconductor memory includes a synchronization signal generation circuit for generating a synchronization signal based on the timing information; and the volatile semiconductor memory operates in synchronization with the synchronization signal.
According to another aspect of the present invention, a semiconductor storage device includes a rewritable non-volatile semiconductor memory and a volatile semiconductor memory, the non-volatile semiconductor memory including: a memory area for storing specification information for specifying a specification of the volatile semiconductor memory; and an output circuit for outputting the specification information stored in the memory area to the volatile semiconductor memory, wherein the volatile semiconductor memory changes the specification of the volatile semiconductor memory based on the specification information.
In one embodiment of the present invention, the non-volatile semiconductor memory further includes another memory area for storing timing information for adjusting a timing of an internal operation of the volatile semiconductor memory; the output circuit outputs the timing information stored in the another memory area to the volatile semiconductor memory; and the volatile semiconductor memory adjusts the timing of the internal operation of the volatile semiconductor memory based on the timing information.
In another embodiment of the present invention, the volatile semiconductor memory includes a synchronization signal generation circuit for generating a synchronization signal based on the timing information; and the volatile semiconductor memory operates in synchronization with the synchronization signal.
In still another embodiment of the present invention, the specification of the volatile semiconductor memory includes a specification as to a bit width of data to be read out from the volatile semiconductor memory.
In still another embodiment of the present invention, the specification of the volatile semiconductor memory includes a specification as to an operating voltage for operating the volatile semiconductor memory.
In still another embodiment of the present invention, the volatile semiconductor memory controls, based on the specification information, an amount of delay in a read timing signal for reading data from the volatile semiconductor memory.
According to still another aspect of the present invention, there is provided a method for evaluating a semiconductor storage device comprising a rewritable non-volatile semiconductor memory and a volatile semiconductor memory, wherein: the non-volatile semiconductor memory and the volatile semiconductor memory are enclosed in a same package; the non-volatile semiconductor memory includes a memory area for storing timing information for adjusting a timing of an internal operation of the volatile semiconductor memory, and an output circuit for outputting the timing information stored in the memory area to the volatile semiconductor memory; and the volatile semiconductor memory adjusts the timing of the internal operation of the volatile semiconductor memory based on the timing information; and the method for evaluating a semiconductor storage device includes steps of evaluating a characteristic of the volatile semiconductor memory, writing the timing information in the memory area, and reevaluating the characteristic of the volatile semiconductor memory.
According to still another aspect of the present invention, there is provided a method for evaluating a semiconductor storage device comprising a rewritable non-volatile semiconductor memory and a volatile semiconductor memory, wherein: the non-volatile semiconductor memory and the volatile semiconductor memory are enclosed in a same package; the non-volatile semiconductor memory includes a memory area for storing specification information for specifying a specification of the volatile semiconductor memory, and an output circuit for outputting the specification information stored in the memory area to the volatile semiconductor memory; and the volatile semiconductor memory changes the specification of the volatile semiconductor memory based on the specification information; and the method for evaluating a semiconductor storage device includes steps of evaluating a characteristic of the volatile semiconductor memory, writing the specification information in the memory area, and reevaluating the characteristic of the volatile semiconductor memory.
In one embodiment of the present invention, wherein: the non-volatile semiconductor memory further includes another memory area for storing timing information for adjusting a timing of an internal operation of the volatile semiconductor memory; and the method for evaluating a semiconductor storage device further includes a step of writing the timing information in the another memory area.
Hereinafter, a function of the present invention is described.
A semiconductor storage device according to the present invention includes a non-volatile semiconductor memory, such as a FLASH EEPROM, and a volatile semiconductor memory, such as an SRAM. The non-volatile semiconductor memory includes: a memory area for storing timing information used for adjusting the internal timing of the semiconductor storage device or information used for changing a specification of the semiconductor storage device; a control circuit for writing information in the memory area (for example, in an example illustrated in FIG. 3, a voltage control circuit, a write control circuit, and the like); and an output circuit for outputting information stored in the memory area (for example, in the example illustrated in FIG. 3, a logic circuit including inverters 12 and 13). The volatile semiconductor memory (SRAM) adjusts an ATD pulse signal generated by a synchronization signal generation circuit (ATD pulse generation circuit) and changes specifications of the SRAM based on the information stored in the memory area of the non-volatile semiconductor memory.
For example, according to the present invention, in semiconductor storage devices arranged for use at 5 V supply voltage specification and 3.3 V supply voltage specification, a memory area for storing information used for switching a specification and a logic circuit are added in the FLASH EEPROM, and a synchronization signal generation circuit for generating the ATD pulse signal based on the information (signal) stored in the memory area is provided in the SRAM, in place of changing of the bonding arrangement or disconnection of a trimming fuse, for the purpose of adjusting a signal which is activated only when the semiconductor storage device operates at the 3.3 V supply voltage.
According to the above semiconductor storage device, a volatile semiconductor memory, such as an SRAM, etc., and a rewritable non-volatile semiconductor memory, such as a FLASH EEPROM, etc., are enclosed in a same package and connected to each other by means of bonding or the like. Thus, writing a signal in the above memory area during or after fabrication of the semiconductor storage device can achieve an effect same as that achieved by disconnection of a fuse or switching of the bonding arrangement. Thus, a malfunction of a device which is caused when a line of device products based on different specifications are produced from a single circuit configuration, or which is caused due to a variation in characteristics of elements constituting the device which occurs during the fabrication process, is eliminated by an adjustment step provided in the first or second half of the fabrication process or provided after the fabrication process, whereby characteristics of the semiconductor storage device can be improved.
Furthermore, a stock step in the manufacturing (production adjustment) can be performed after the fabrication process is completed. As a result, the number of products which may be disposed of as defective products in the first and second half of the fabrication process can be reduced. Furthermore, there is no possibility that an unsuccessful disconnection of a trimming fuse by a laser beam is caused. Similarly, an unsuccessful bonding in a bonding step can be avoided. Further still, an adjustment step can be performed after a step for evaluating characteristics. Thus, fabrication of products for sale can be started at an earlier stage in the entire manufacturing process, and accordingly, a period required for experimental production and a period required for evaluation of a product can be shortened.
In the case where various types of devices are produced from a same chip design, if a deviation of the internal timing of the device is expected before fabrication, a pulse width adjustment signal may be associated with a signal for changing the device type (specification), whereby concurrently with the switching of the device type, the pulse width can be adjusted so as to be optimum for a selected device type. Furthermore, even after the quantity of production has been increased, it is possible to quickly satisfy demands of customers because a stock step for products is performed only for finished products after the fabrication process has been completed.
Thus, according to the present invention, adjustment for a deviation of a word line selection signal and a deviation of a sense amplifier enable signal from the internal timing which result from variation of characteristics caused during the fabrication process, change of various functional specifications (e.g., between a product having 8-bit input/output terminal and a product having 16-bit input/output terminal), and change in the supply voltage specification (e.g., between a 5 V specification and a 3.3 V specification), all of which can be achieved before a packaging step has been completed in a conventional semiconductor storage device, can be achieved even after the packaging step has been completed. Furthermore, such adjustment and change in specifications can be achieved only inside the semiconductor storage device, and accordingly, the configuration of terminals of the device is the same as those of conventional, widely-used semiconductor storage devices. Therefore, customers need not change a conventional system design. Further still, a conventional, widely-used non-volatile semiconductor memory such as a FLASH EEPROM has a terminal for introducing an internal timing adjustment control signal and an internal timing adjustment write signal into the FLASH EEPROM, and therefore, it is not necessary for the semiconductor storage device of the present invention to provide additional terminal therefor.
Thus, the invention described herein makes possible the advantages of (1) providing a semiconductor storage device having a configuration of terminals which is the same as those of conventional, widely-used semiconductor storage devices where, after the fabrication process of the semiconductor storage device is completed, specifications for functions or specifications for performance can be changed, and a deviation of the internal timing of the semiconductor storage device which results from a variation of characteristics caused during a fabrication process thereof can be eliminated; and (2) providing a method for evaluating such a semiconductor storage device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.